The semiconductor device industry has a market driven need to reduce the time required for signals to travel between integrated circuits (ICs), such as the high number of relatively low cost memory chips used in virtually every electronic device. One method known to reduce signal travel time is to reduce the physical distance between closely related IC chips by attaching them together in a vertical stack. This reduces the distance the signals travel as well as reducing electrical resistance, inductance and capacitance, resulting in faster systems using IC technology.
There is an industry wide issue in stacking ICs such as memory chips and logic chips, and interconnecting the ICs to reduce the capacitance for fast inter-chip communication. Current methods of connecting similar Input/Output (I/O) pads on stacked chips, such as using wire bonds, share all of the I/O pads for all of the chips in the vertical stack. This may increase the capacitance between the interconnected I/O pads.